Course Description
This on-site, intensive 4- or 5-day course provides a comprehensive, broad but detailed examination of current silicon wafer fab process technology, from Si crystal growth through Parametric Test. Learn the details – the why and the how – of all individual wafer fab process techniques, including:
A baseline CMOS process flow will provide a clear introduction to process integration principles and the context for discussion of these process techniques.
The rapid and continuous scaling of devices, from the 0.25 um technology node of 25 years ago to today’s new 5 nm and 3 nm processes, has necessitated and driven evolutionary and revolutionary changes to fab equipment, process integration, and process techniques. This course will discuss why and how these changes have occurred, and the whys and hows of newer and leading-edge techniques, including:
- Thermal Processing
- Ion Implantation
- Wafer Cleaning and Surface Preparation
- CVD (Chemical Vapour Deposition)
- Epitaxy
- PVD (Physical Vapour Deposition)
- Lithography
- Etch
- CMP (Chemical-Mechanical Planarization)
- ECD (Electrochemical Deposition)
- ALD (Atomic Layer Deposition)
A baseline CMOS process flow will provide a clear introduction to process integration principles and the context for discussion of these process techniques.
The rapid and continuous scaling of devices, from the 0.25 um technology node of 25 years ago to today’s new 5 nm and 3 nm processes, has necessitated and driven evolutionary and revolutionary changes to fab equipment, process integration, and process techniques. This course will discuss why and how these changes have occurred, and the whys and hows of newer and leading-edge techniques, including:
- continuous Czochralski silicon growth
- cluster beam ion implantation
- cryokinetic and SCCO2 cleaning
- plasma doping and GILD (gas immersion laser doping)
- flash annealing and laser spike annealing
- ultra high density plasma etching
- SOI (silicon on insulator) technology
- lithography RETs (resolution enhancement techniques)
- immersion and EUV lithography
- metal gate options
- strained silicon
- 3D finFET and GAA (gate all around) transistors
- 3D NAND flash memory
Who Should Attend
This course is designed for semiconductor industry professionals who wish to enhance or update their knowledge of silicon wafer fabrication process technology. These include:
- wafer fab process engineers/technologists, yield engineers, equipment engineers
- scientists, engineers and technologists from wafer fab equipment and materials suppliers
- equipment/materials sales/marketing experts
- process integration engineers
- process analysts
- "back-end" engineers: product engineers, test engineers, packaging engineers
- materials scientists
- technical managers
Course Notes
Participants will receive a PDF containing all PowerPoint slides. These highly detailed slides will minimize the need for note-taking during class and will serve as an excellent post-course reference.
Course Fees and Additional Information
To schedule this course at your site or for additional information, including course fees, please contact JFTS.
Course Reviews
To read some comments from past participants, please see course reviews.